The primary goal of static timing analysis (STA) is to verify the timing correctness of integrated circuits. Conventional static timing analysis, however, does not take into account the effect of coupling noise on timing.
Coupling capacitance exists when two neighboring wires in an integrated circuit are in close proximity to each other. Depending on how the signals rise or fall on these wires, capacitive coupling can cause changes in the delays and slews (transition times) of gates and wires. For example, if the signals on the two neighboring wires are switching in the same direction (i.e., both rising or both falling), then the coupling capacitances between the two wires have their two terminal voltages moving in the same direction; hence the effective capacitance is reduced due to the so-called Miller effect, which causes the signals to speed up. Alternatively, if the two signals are switching in opposite directions, the effective capacitance is exacerbated, which can cause the signals to slow down. Taking into account these coupling effects is essential to correctly predict the timing characteristics of integrated circuits. With advanced technologies, coupling between wires is increasing, since the wires in modern integrated circuit technologies are taller and thinner than ever before, and high packing densities lead to wires that are closer to each other and to a larger number of on-chip interconnections.
Coupling in the form of interactions between adjacent wires causes disturbances that are not easily handled by a conventional static timing analysis. This is because static timing relies on levelization of the timing graph, whereas due to coupling, gates and wires at different level numbers can impact each others' delays and slews. Although some methods are known for analyzing coupling effects in STA, these prior-art methods do not take process variations into account.
With each new generation of integrated circuit technology, variability (e.g., due to process parameters, environmental parameters and aging effects, hereinafter collectively referred to as “process parameters”) is proportionately increasing. To handle this increased variability in STA efficiently and with reduced pessimism compared to corner-based (or deterministic) timing methods, statistical timing is often used. Statistical timing analysis is static timing analysis that accounts for process variation; as used herein, the terms “static timing analysis”, or simply “timing analysis”, are understood to include statistical timing analysis.
Variations also impact coupling noise, and hence the change of timing characteristics due to coupling effects. Treating coupling effects in a corner-based fashion (i.e., conducting the timing analysis with coupling considerations at one or more chosen deterministic settings of all process parameters) is pessimistic as well as inefficient. Thus prior-art methods cannot accommodate both coupling events and process variations in an efficient or accurate manner.
FIG. 1, for example, is a schematic diagram illustrating an exemplary coupling event 100. As illustrated, first and second neighboring wires (or nets) 102a and 102b on a chip have coupling between them. A signal on the first wire 102a is driven by a first gate 104a and received by a second gate 106b. The second wire 102b is driven by a third gate 104b and received by a fourth gate 106b. When the signals driven through two neighboring wires, such as the first wire 102a and the second wire 102b, switch during the same time window, this is referred to as a coupling event.
The wire at which a signal is being analyzed for timing is referred to as the “victim,” while the wire with which the victim experiences a coupling event is referred to as the “aggressor.” Thus, for instance, if one is interested in the timing of the signal driven along the first wire 102a, then the first wire 102a is the victim, and the second wire 102b is the aggressor. The signal at the output of the first gate 104a is called the near-end victim signal and the signal at the input of the second gate 106a is called the far-end victim signal. Likewise, the signal at the output of the third gate 104b is called the near-end aggressor signal and the signal at the input of the receiver fourth gate 106b is called the far-end aggressor signal. If the signal driven through the aggressor switches contemporaneously and in the same direction as the signal driven through the victim, then the transmission of the signal on the victim will be sped up. Alternatively, if the signal driven through the aggressor switches contemporaneously and in the opposite direction of the signal driven through the victim, then the transmission of the signal through the victim will be slowed down.
FIG. 2 illustrates an electrical equivalent circuit 200 for the exemplary coupling event illustrated in FIG. 1. The first and second wires 102a and 102b have been modeled by resistance and capacitance (RC) parasitics, typically produced from the layout of the integrated circuit by an extraction program. The coupling capacitances are shown in bold lines. Four factors influence the change of delay due to a coupling event. The first factor is whether or not the two signals at the two terminals of any of the coupling capacitances overlap (i.e., can the signals transition contemporaneously or during the same window of time?), as well as the amount of time during which the signals can overlap. The second factor is the amount of coupling capacitance. The third factor is the transition time or slew of signals at the aggressor near-end, aggressor far-end, victim near-end and victim far-end. Finally, the fourth factor is the strength of the victim and the strength of the aggressor, which includes the sizes of the driving gates (e.g., first and third gates 104a and 104b) and the power supply voltage swings of the victim and aggressor driver gates (e.g., first and third gates 104a and 104b). In the face of process variations, all of these quantities are statistical in nature.
In reference to FIG. 2, several important drawbacks of deterministic timing and deterministic coupling analysis are described below. A first drawback is that predicting the worst-case corner (or setting of process parameters that produces the worst-case timing result) is not immediately obvious, since when process parameters vary, some of the factors described above make the coupling event worse, and some factors make it better. For example, suppose that, due to process variations, the victim driving gate strength is diminished. As a result of this variation, the victim near-end and far-end signals arrive later. One possible result is an overlapping time window between the victim and aggressor, which will make the coupling event worse. A different, but also possible, result is that there will no longer be an overlapping time window, which will make the coupling event better.
A second drawback is that using a worst-case analysis is needlessly pessimistic. For example, suppose again that, due to process variations, the victim driving gate strength is diminished. As a result, the victim near-end and far-end signals arrive later, and perhaps there will be no overlapping time window between the aggressor and victim. On the other hand, if the victim driving gate is stronger, the impact of the noise coupling event will be diminished, since the strong driving gate will drive the wire in a stronger fashion. A simple worst-case analysis will not take these correlations into account and will predict a needlessly pessimistic result.
A third drawback is that for a thorough analysis, several combinations of process variations must be analyzed. For example, weak and strong drivers, thin and thick metal layers, high and low voltage supplies, and all combinations thereof should be examined for a thorough analysis. Such an exhaustive analysis, however, is inefficient.
Thus, there is a need for a method and an apparatus for static timing analysis in the presence of a coupling event and process variation.